Conventionally, 1-transistor, 1-capacitor (hereinafter referred to as "1Tr-1C") type cells are widely used for dynamic MOS RAMs. FIG. 1 shows a cross-sectional view of a typical example of a 1Tr-1C type cell. In the Figure, the reference numeral 1 designates a bit line electrode, the numeral 2 designates a word line electrode, the numeral 3 designates a cell plate electrode, the numeral 4 designates a diffusion layer, the numerals 5 and 6 designate oxide films, the numeral 7 designates a storage node, and the numeral 8 designates a substrate. The elements 1, 2, 4, and 5 constitute a MOS transistor, and the elements 3, 6, and 7 constitute a MOS capacitor.
The cell plate electrode 3 is usually connected to the ground level or a power supply voltage. In the 1Tr-1C type cells carriers are stored at the inverted layer of the storage node 7, and the equivalent circuit thereof is shown in FIG. 2. In FIG. 2, the numeral 9 designates a MOS capacitance, and the numeral 10 designates a junction capacitance between the inverted layer and the substrate 8. The junction capacitance 10 is usually about 20% of the MOS capacitance 9.
With the increase of the capacity of dynamic RAMs, the cell area decreases and the MOS capacitance 9 and the junction capacitance 10 also decrease. Against this problem, there is an attempt to use a thin film as the oxide film below the cell plate in order to secure the storage capacitance. However, the breakdown voltage decreases with the decrease of the film thickness, thereby lowering the reliability. As a countermeasure against this problem, there is a measure to make the voltage of the cell plate 3 a half value of the voltage to be written into the storage node 7. This lowers the voltage applied to the gate oxide film 6 to a half value, thereby improving the breakdown voltage to a great extent.
There are two types of circuits, for example, a resistor (11, 12) dividing circuit shown in FIG. 3 and a MOS transistor (13) dividing circuit shown in FIG. 4 which realize the half voltage value of the writing voltage in a dynamic RAM having a single power supply voltage of 5 V. However, the output resistances will necessarily become high caused by the restrictions in stand-by currents of the dynamic RAMs or the restrictions in transistor sizes in both cases of using the circuits of FIGS. 3 and 4.
In dynamic RAMs where the substrate voltage is generated inside a chip as mainly used recently, when the cell plate exhibits an electrically high resistance against the ground level or the power supply voltage, it is likely to lose the storage charge in the memory cell.
The above-described disadvantage is described in greater detail, in the following:
Usually the substrate voltage is generated by a charge-pump circuit shown in FIG. 5. In FIG. 5, the numeral 14 designates a MOS transistor, the numeral 15 designates a capacitor, the numeral 16 designates an oscillator, and V.sub.BB designates a substrate voltage. The operation of the charge-pump circuit is well known, and the description thereof is abbreviated for simplicity. The voltage V.sub.BB generated by this circuit is electrically floating with respect to the voltages generated by external power supplies, and it is likely to be subjected to variations by such as capacitance coupling.
In the operation of a dynamic RAM charging and discharging are repeated, and when the junction capacitances associated with a lot of transistors are charged or discharged at once, the substrate voltage varies caused by the capacitance couplings of the junction capacitances.
FIG. 6 shows typical waveforms of signals including the substrate voltage in an operation of a dynamic RAM. In the Figure, WL designates a word line signal, SE designates a sense signal, and V.sub.BB designates a substrate voltage.
After the external RAS signal falls, the word line WL rises, and the information of the memory cell is transmitted to the bit line. Thereafter, the sense signal SE rises, and the bit line is sensed. Then, all the bit lines are sensed at once in usual dynamic RAMs, and charges at the large junction capacitance associated with all the bit lines are discharged, and by this capacitor coupling the substrate voltage V.sub.BB varies in the direction of a negative voltage. When the external RAS signal rises thereafter, the word line WL falls. Thereafter, all the bit lines are pre-charged. Then, the substrate voltage varies in the opposite direction, that is, the direction of positive voltage.
FIG. 7 shows potential levels for electrons in the memory cell portion of the dynamic RAM. SN shows potential levels for the storage node, WL shows those for the word line, and BL shows those for the bit line.
The operation before variation is described as follows:
L shows a potential level when a low level is written in, and electrons are filled up to that level. H shows a potential level when a high level is written in, and electrons are filled up to that level. The difference between the "L" and "H" states corresponds to the difference of the quantity of storage charges. The "ON" state of WL means that the word line is opened, whereby it is possible for the potential level to fall to the high level "H" to be written into the storage node. The "OFF" state of WL means that the word line is closed, whereby the storage node and the bit line are cut off from each other.
Now suppose that the bit line BL is sensed, a low or high level signal is stored in the storage node, and the word line WL is closed. Then, the substrate voltage varies in the direction of positive voltage, and the voltage at the storage node varies to the positive voltage side to the extent obtained by dividing the variation of the substrate voltage by the junction capacitance 10 and the MOS capacitance 9 shown in FIG. 2. In this state, both potentials of the low and high levels fall as shown in FIG. 7 as after variation. When the word line rises in the next cycle, the potential of the word line falls only up to the high level "H" before variation, whereby the quantity of charges read out after variation decreases as shown by hatching in FIG. 7. The extent of this decrease is as great as the variation of the substrate voltage. Ihe variation of the substrate voltage depends on the junction capacitance which gives rise to a capacitance coupling, and on the stray capacitance between the substrate and ground level and between the substrate and the power supply level. That is, as the stray capacitance is great, the variation of the substrate voltage becomes small. The stray capacitance of the substrate itself is the sum of the junction capacitances of the diffusion layers of the ground line and of the power supply line, the capacitance between the substrate and ground through the junction capacitance of the bit lines, the capacitance between the substrate and ground through the junction capacitance of the storage node, and the MOS capacitance. In large capacity memories, the proportion of the capacitance between the substrate and ground through the junction capacitance of the storage node and the MOS capacitance among the capacitances amounts to a large value of about 50%.
As shown in the memory cell equivalent circuit of FIG. 2, the capacitance per memory cell between the substrate and the ground through the junction storage node is equal to a serial sum of the junction capacitance 10 and the MOS capacitance 9. The junction capacitance 10 is about 20% of the MOS capacitance 9, and the capacitance between the substrate and ground becomes approximately equal to the junction capacitance 10.
However, when a half voltage of the writing voltage is applied to the cell plate, the cell plate exhibits an electrically high-resistance against ground as already described. In that case, the MOS capacitance 9 against ground becomes small effectively, whereby the MOS capacitance 9 can not be ignored. As result, the capacitance per a memory cell between the substrate and ground through the storage node decreases to well below the junction capacitance 10.
Thus, the stray capacitance of the substrate itself decreases, and the variation of the substrate voltage due to the charging and discharging of the bit line becomes large. The variation will amount to 2 or 3 times the substrate voltage.
As described above, there is a disadvantage that the operational margin of the dynamic RAM decreases due to the loss of the quantity of the storage charges when a half voltage of the writing voltage is applied to the cell plate in a semiconductor memory device including a substrate voltage generating circuit.
Another prior art dynamic memory device is described in U.S. Pat. No. 4,240,292 entitled "RANDOM ACCESS MEMORY CELL WITH DIFFERENT CAPACITOR AND TRANSISTOR OXIDE THICKNESS". In this patent, it is disclosed that it is possible to increase the storage capacitance with the use of a thin oxide film by decreasing the cell plate voltage (for example, up to about 1/2 of the writing voltage), and thereby decreasing the electric field applied to the oxide film.
Another prior art dynamic memory cell is disclosed in an article "Single 5 V, 64K RAM with Scaled-Down MOS Structure" HIROO MASUDA et al. IEEE TRANS. ELECTRON DEVICES. vol. ED-27, No.-8, pp. 1607-1612, Aug., 1980. In this article, it is disclosed that in a dynamic RAM including a substrate voltage generating circuit the S/N ratio is lowered due to the variation of the substrate voltage which is caused by the capacitance coupling of the junctions constituting the bit lines and the decoders which occurs during the charging and discharging of the bit line and the decoder.
Yet another prior art dynamic RAM is disclosed in an article "A 5 V-only 64K Dynamic RAM" Lionel S. White et al., ISSCC Dig. Tech. Papers, pp. 230 to 231, Feb., 1980. In this article it is disclosed that it is possible to suppress the variation of the substrate voltage by making the substrate voltage the ground level.